The present invention relates to the design of an integrated circuit, and more specifically, to virtual sub-net based routing in integrated circuit design.
As part of the design of an integrated circuit, interconnections among the various sub-networks or sub-nets (groupings of transistors and other components) must be routed. Two considerations in determining the routes are timing and crosstalk. For example, if the routes are too long, timing constraints of the design may not be met. As another example, when routes are temporally aligned, crosstalk may occur such that a signal on one route affects or interferes with a signal on another route. Temporal correlation of interconnects refers to transitions (0 to 1 or 1 to 0) occurring around the same time in close by interconnects.